A ferroelectric memory device has a non-volatile property to retain previous data even when a power supply is interrupted. Similar to a dynamic random access memory (DRAM) or a static random access memory (SRAM), the ferroelectric memory device operates at a relatively low power supply voltage. For these reasons, the ferroelectric memory device may be a promising candidate for use in applications such as smart cards.
A conventional method of fabricating a ferroelectric memory device is now described below with reference to FIG. 1 through FIG. 3. Referring to FIG. 1, device isolation layers 13 are formed at predetermined regions of a semiconductor device to define an active region therebetween. A plurality of insulated gate electrodes 15 (providing wordlines) are formed across the active region and the device isolation layer 13. Impurities are implanted into portions of the active region between gate electrodes 15 to form source/drain regions 17s and 17d. A first lower interlayer dielectric 19 is formed on a surface of the structure including source/drain regions 17s and 17d, device isolation layers 13, and gate electrodes 15. The first lower interlayer dielectric 19 is patterned to form storage node contact holes exposing the source regions 17s. Contact plugs 21 are formed in the storage node contact holes.
Referring to FIG. 2, ferroelectric capacitors 32 are formed on predetermined regions of the structure including the contact plugs 21. Each of the ferroelectric capacitors 32 includes a lower electrode 27, a ferroelectric pattern 29, and an upper electrode 31 which are sequentially stacked. The lower electrodes 27 cover their respective contact plugs 21. An inter-metal dielectric 33 is formed on a surface of the structure including the ferroelectric capacitors 32. Typically, the inter-metal dielectric 33 is made of silicon oxide.
Referring to FIG. 3, the inter-metal dielectric 33 is planarized down to a top surface of the upper electrode 31 to provide an inter-metal dielectric pattern 33′. To planarize the inter-metal dielectric 33, an etch-back process or a chemical mechanical polishing (CMP) process is carried out.
After planarization, a deposition thickness and an etch thickness may vary across different positions on a wafer. That is, the inter-metal dielectric 33 may be less etched at dotted circle 38 so that the upper electrode 31 is not exposed at dotted circle 38, as shown in the FIG. 3. In this case, the upper electrode 31 of ferroelectric capacitor 32 may be electrically isolated, thereby preventing proper operation. To address this situation, the inter-metal dielectric 33 may be overetched in the planarization process. However, the foregoing deviation in deposition and etch thickness may result in the inter-metal dielectric pattern 33′ being overetched to expose the ferroelectric pattern 29 at dotted circuit 39. The exposure of the ferroelectric pattern 29 may give rise to deterioration of operation characteristics of the ferroelectric capacitor 32.
Reducing deviations in thicknesses of an inter-metal dielectric may be difficult due to limitations of processing tolerances of existing processing technologies. A realizable approach may be to form an upper electrode whose thickness is greater than a maximum thickness deviation across a wafer. This approach may reduce problems associated with the thickness deviations, but may cause the ferroelectric capacitor 32 to be thicker. The thicker the ferroelectric capacitor 32 is, the more difficult vertically patterning a sidewall of the ferroelectric capacitor 32 may become.